The present invention relates to a semiconductor device and a manufacturing method for semiconductor device. More particularly, the invention relates to a capacitor having a triple diffusion barrier layer and a manufacturing method this kind of capacitor.
When used in a memory device, a capacitor must have an appropriate capacitance to smoothly operate the device. In DRAMs, the important factors involved in determining the required capacitance of the capacitor are its refresh errors and soft errors. These two factors are derived, respectively, from leakage current and from the alpha particles emitted from metal wiring. Each of these two factors exerts an adverse influence on the correct maintenance of the data stored in a memory cell. A capacitor in a memory device must have a capacitance large enough to retain a sufficient charge despite refresh and soft errors.
As DRAM integration level increases, the area that a capacitor can occupy in a cell correspondingly decreases. However, the capacitance required in a capacitor of a highly integrated memory cell does not decrease. In a 256-Mbit DRAM, for example, a capacitance of approximately 25 fF is required to prevent operational errors caused by the refresh and soft errors. A capacitor in a DRAM device must achieve the required capacitance while remaining within the limited area allowed for it in its memory cell.
In general, the capacitance C of a capacitor is given by the formula: ##EQU1## here s is the surface area of a storage node in the capacitor, .epsilon. is the dielectric constant of a dielectric, and d is the thickness of the dielectric. Traditionally, capacitors were made of two parallel nodes, with the direct surface area of the storage node being used in the above equation.
In a small-area memory cell, however, a three-dimensional storage node structure such as a stacked node or a trench node may be adopted for a capacitor in a highly-integrated s memory cell to increase the effective surface area of the capacitor. In a DRAM of 64-Mbit or above, a three-dimensional storage node structure even more complicated than a stacked or trench node, e.g., a cylinder structure or a fin structure, is required to ensure a sufficiently large effective surface area for the capacitor. In a DRAM of 256-Mbit or above, which has a severe limit on the width of the capacitors, an available area of the capacitor must be further increased by raising the height of the three-dimensional storage node to a point high enough to provide the needed capacitance of 25 fF. Unfortunately, this requirement has the effect of lowering the production yield of a memory cell and raising the ultimate process cost by increasing the number of process steps required to make a capacitor. The number of steps increases because fine feature processing technology becomes necessary for the formation of the capacitor or an upper wiring when the storage node gets too high. It is therefore desirable to find a way to increase capacitance without increasing the height of a capacitor.
As can be seen from the above capacitance equation, for the capacitance to increase, the dielectric constant (.epsilon.) or the effective surface area (s) of the capacitor must increase or the thickness (d) of the dielectric must decrease. The effective surface area of the capacitor is limited by the height and width of the capacitor as discussed above. The remaining elements of the equation depend upon the type of dielectric used. For example, the minimum thickness of the dielectric in the capacitor depends on the properties of the dielectric. Thus, to increase the capacitance, the dielectric can be chosen to have properties that reduce its minimum thickness. Alternatively, a dielectric having a high dielectric constant can be chosen. In either case, the capacitance of the memory cell capacitor will be increased.
In a 1-Mbit DRAM cell, an oxide film is grown on a semiconductor substrate and used as the dielectric film for the capacitors. In a 4-Mbit DRAM cell, a nitride film having a dielectric constant about twice that of the oxide film is used as the dielectric instead of the oxide film to increase cell reliability. In a 256-Mbit DRAM, it is necessary to use a dielectric having a larger dielectric constant than the oxide and nitride films. A dielectric with a small dielectric constant would impose unreasonable constraints on the fabrication process and manufacturing process technology of the capacitor. Currently, Ta.sub.2 O.sub.5, PZT, SrTiO.sub.3 and (Ba, Sr)TiO.sub.3 (more simply, BST) are being explored as materials having sufficiently large dielectric constants for a 256-Mbit DRAM.
Ta.sub.2 O.sub.5, for example, has a dielectric constant of about 20. To use this material for a 256-Mbit DRAM, a complex three-dimensional storage node structure like a cylinder or fin structure must be used. This has the disadvantage that it does not avoid complexity in the manufacturing of the capacitor.
PZT also has a large dielectric constant, but has the disadvantage that it is ferroelectric. This can lead to degradation of polarization reversal in the memory cell. As a result, an appropriate cell circuit design must be made or some other measure must be taken to avoid this problem before PZT can be used in a 256-Mbit DRAM.
The dielectric constant of BST is higher than that of Ta.sub.2 O.sub.5, and BST is not appreciably ferroelectric at the operating temperature of a general device. As a result, a desired capacitance can be obtained with BST even using a simple stacked storage node in a 256-Mbit DRAM cell.
Nevertheless, BST does have some disadvantages. If, when using a BST film as a high dielectric film, a current storage node is formed of silicon, then an oxide film may be formed at the interface of the BST film and the storage node in the subsequent annealing process. This can lead to a decrease in the capacitance of the capacitor. To avoid this problem, a storage node is generally formed of a refractory metal such as platinum (Pt) when using BST as a high dielectric film. Unfortunately, Pt reacts with the silicon, the interface between the two becomes unstable, and silicon atoms diffuse through the Pt film into the BST film, thereby decreasing the dielectric constant of the BST.
To circumvent this problem, an appropriate diffusion barrier layer must be formed between a Pt electrode and a silicon layer. In a capacitor having a conventional diffusion barrier layer a Ti or TiN thin film is used, for example, "A Memory Cell Capacitor with Ba.sub.x Sr.sub.1-x TiO.sub.3 (BST) Film for Advanced DRAMS," Symposium on VLSI Technology Digest of Technical Papers (1994). However, the Ti in each of these films may be oxidized by diffused oxygen. The oxygen atoms can pass through the Pt film and react with the Ti and TiN to produce a TiO.sub.x oxide and nitrogen gas. In addition, when a TiN thin film is used, the nitrogen gas resulting from the oxidation of the Ti is trapped at the interface of the Pt and TiN, thereby making the Pt film partially swollen, making its surface rough, and locally lifting it off the substrate. The lift-off becomes severe when oxygen ions activated in the course of forming the BST film are generated. Furthermore, the lift-off takes place regardless of the thickness of the Pt and regardless of any prior processing of the TiN.
A capacitor manufacturing method in which the Ti film or TiN film is used as a diffusion barrier layer will be described in detail, referring to the attached drawings. FIGS. 1 to 3 illustrate the steps of this process in a conventional capacitor manufacturing method.
FIG. 1 shows the step of forming a first insulating film including the formulation of a contact hole. In this example, a borophosphosilicate glass (BPSG) film is formed as first insulating film 3 on a semiconductor substrate 1 having a transistor formed therein by a usual method. A photoresist (not shown) is formed on the overall surface of the first insulating film 3, from which a photoresist pattern 4 is formed to define a contact hole 7. The first insulating film 3 is then dry-etched, using photoresist pattern 4 as a mask, to form the contact hole 7. Afterwards, a spacer 5 is formed on the inner wall of the contact hole 7 and the photoresist pattern 4 is removed.
FIG. 2 shows the step of sequentially forming a diffusion barrier layer and a lower storage node. In more detail, a polysilicon layer (not shown) doped with a conductive impurity is formed on the overall surface of semiconductor substrate 1 including contact hole 7. Thereafter, the overall surface of the polysilicon layer is etched back and planarized. The etch-back is performed until the surface of first insulating film 3 is entirely exposed. As a result, the polysilicon layer on the first insulating film 3 and around the contact hole 7 is completely removed, and only the contact hole 7 remains filled with the polysilicon. This polysilicon in the contact hole 7 becomes a first conductive layer 9. Next, a double diffusion barrier, formed of first and second layers 11 and 13, is sequentially formed over the surface of semiconductor substrate 1 including the first conductive layer 9. Then, a second conductive layer 15 is formed on the diffusion barrier 11 and 13. Thereafter, a photoresist 17 is deposited to cover the second conductive layer 15.
The first and second layers 11 and 13 of the diffusion barrier can be a titanium (Ti) layer and a nitride titanium (TIN) layer, respectively. The second conductive layer 15 is preferably formed of Pt and acts as the lower storage node of the capacitor.
FIG. 3 shows the step of forming an upper storage node. First, the photoresist 17 shown in FIG. 2 is patterned. Then the second conductive layer 15 and the diffusion barrier layer 11 and 13 are anisotropically etched using the photoresist pattern as a mask. As a result, a second conductive layer pattern 15a and a diffusion barrier layer pattern 1 la and 13a are formed. The anisotropic etching is performed until it reaches the surface of first insulating film 3. A second insulating film 19 is then formed by a sputtering method on the surface of the semiconductor substrate 1 including the resultant patterned structure. The second insulating film 19 is then annealed. After the annealing, a third insulating film 21 is formed on the overall surface of second insulating film 19. The third insulating film 21 acts as the upper storage node of the capacitor and is formed of Pt.
In this conventional capacitor manufacturing method, sufficient capacitance can be obtained using a simple stacked storage node in a capacitor since BST, which has a high dielectric constant, is used as the dielectric film. However, due to the oxygen atoms generated in the annealing step, a metal oxide (TiO.sub.x) and nitrogen gas are both formed in the interface between the lower storage node of the capacitor (second conducting layer 15a) and the portion of the TiN film forming a patterned second layer 13a in the patterned diffusion barrier. The nitrogen gas becomes trapped at the interface of the lower storage node and the TiN film, thereby making the lower storage node partially swollen and its surface rough. As a result of this, the capacitance of the capacitor is undesirably decreased.
One option the inventors pursued to solve this problem was to oxidize a portion of the TiN layer to prevent further oxidation of Ti through the reaction of the TiN and oxygen atoms. By completely oxidizing the TiN in advance, the above problem can be avoided. However, this raises the additional problem of undesirably increasing the resistance of the TiN thin film.